As one of semiconductor device substrates, there is an SOI substrate having a silicon layer (which may be referred to as an SOI layer hereinafter) formed on a silicon oxide film as an insulator film. This SOI substrate has characteristics such as a small parasitic capacitance or a high radiation-proof ability since the SOI layer in a substrate surface layer portion serving as a device fabrication region is electrically isolated from the inside of a substrate by a buried oxide film layer (a BOX layer). Therefore, effects such as a high speed/low power consumption operation or prevention of soft-error can be expected, and this substrate has promise as a high-performance semiconductor device substrate.
As a method for manufacturing this SOI substrate, the following method is known, for example. That is, two mirror-polished single-crystal silicon substrates (a single-crystal silicon substrate that becomes an SOI layer (a bond wafer) and a single-crystal silicon substrate that becomes a support substrate (a base wafer)) are prepared, and an oxide film is formed on a surface of at least one silicon substrate. Further, these single-crystal silicon substrates are bonded to each other via the oxide film therebetween, and then a heat treatment is carried out to increase bonding strength. Then, a film thickness of the bond wafer is reduced to obtain an SOI substrate having an SOI (Silicon On Insulator) layer formed therein. As a method for this film thickness reduction, there is, e.g., a method for grinding or polishing the bond wafer until a desired thickness is obtained, or a method for delaminating the bond wafer at an ion implanted layer based on a method called an ion implantation and delamination method.
As explained above, the SOI substrate has many structural merits in view of electrical characteristics but has structural demerits in terms of resistance against metal impurity contamination.
That is, in many cases, a diffusion rate of a metal impurity is slow in the silicon oxide film rather than in silicon. Therefore, when contamination spreads from a surface of the SOI layer, the metal impurity hardly passes through the BOX layer, and hence it is stored in the thin SOI layer. Therefore, a harmful effect of the metal contamination becomes more serious as compared with that in a silicon substrate having no SOI structure. Therefore, in case of the SOI substrate, having an ability of capturing the metal impurity and removing it from a region serving as an active layer of a semiconductor device (a gettering ability) is one of more important qualities.
According to gettering techniques (e.g., oxide precipitates, high-concentration boron addition, or a polysilicon film on a back surface) that are generally used in case of a silicon substrate having no SOI substrate, a gettering layer is introduced on a substrate side opposite to an active layer. However, even if the same techniques are used to introduce the gettering layer on a support substrate side in the SOI substrate, since a metal impurity hardly passes through the BOX layer, there is a problem that the gettering layer does not sufficiently function, and these techniques cannot be applied to the SOI substrate as they are.
To solve such problems, several methods for introducing a gettering region near an SOI layer of an SOI substrate have been conventionally proposed.
For example, Japanese Patent Application Laid-open No. 1994-163862 or Japanese Patent Application Laid-open No. 1998-32209 discloses a method for providing a region containing an impurity such as phosphorus or boron at a high concentration for gettering. However, such a method has a problem that an increase in the number of processing steps of introducing the impurity results in a rise in cost and a reduction in productivity. Furthermore, when the impurity introduced for gettering diffuses to reach an active layer of a semiconductor device due to a heat treatment in a manufacturing process of the SOI substrate or in a device process, a harmful effect on electrical characteristics is concerned.
Moreover, as another method, Japanese Patent Application Laid-open No: 1994-275525 discloses a method for forming a polysilicon layer in an SOI layer region near an interface between an SOI layer and a BOX layer to getter a metal impurity. However, this method likewise has a problem that an increase in the number of processing steps of forming the polysilicon layer results in a rise in a cost and a reduction in productivity. Additionally, when a thickness of the SOI layer is small, forming the polysilicon layer is very difficult.